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PRELIMINARY
DS1254 2M x 8 NV SRAM with Phantom Clock
www.dalsemi.com
FEATURES
Real time clock keeps track of hundredths of seconds, seconds, minutes, hours, days, date, months, and years with automatic leap year compensation valid up to the year 2100 2M x 8 NV SRAM Watch function is transparent to RAM operation Automatic data protection during power loss Unlimited write cycle endurance Surface-mountable BGA module construction Over 10 years of data retention in the absence of power Battery monitor checks remaining capacity daily +3.3V or +5V operation
PACKAGE OUTLINE
(Side -A- Shown) (For Reference Only Not To Scale)
BGA Module Base Bottom View
ORDERING INFORMATION
PART # DS1254X DESCRIPTION 2M X 8 NV SRAM with Phantom Clock W +3.3V operation Y +5.0V operation
PIN DESCRIPTION
VCC A0-A20 DQ0-DQ7
CE
OE WE BW
GND
- Supply Voltage - Address Inputs - Data I/O - Chip Enable Input - Output Enable Input - Write Enable Input - Battery Warning Output (Open Drain) - Ground
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060800
DS1254
DESCRIPTION
The DS1254 is a fully static nonvolatile RAM (organized as 2M works by 8 bits) with built-in real time clock. The DS1254 has a self-contained lithium energy source and control circuitry which constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs, the DS1254 makes use of an attached DS3800 Battery Cap to maintain clock information and preserve stored data while protecting that data by disallowing all memory accesses. Additionally, the DS1254 has dedicated circuitry for monitoring the status of an attached DS3800 Battery Cap. The Phantom Clock provides timekeeping information including hundredths of seconds, seconds, minutes, hours, day, date, month, and year information. The date at the end of the month is automatically adjusted for months with less than 31 days, including correction for leap years. The phantom clock operates in either 24-hour or 12-hour format with an AM/PM indicator.
Pin Assignment Figure 1
Because the DS1254 has a total of 168 balls and only 35 active signals, balls are wired together into groups, thus providing redundant connections for every signal.
A10 A11 GND A12 A13 A14 A15 A16 31 VCC VCC 30 A8 40 A9 39
VBAT 41 38 37 36 35 34 33 32
VCC A7 A6 A5 GND A4 A3 A2 A1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Receptacles for DS3800 Battery Cap pins
29 28 27 26 25 24 23 22 21
VCC A17 A18 A19 GND A20 CE OE WE
GND GND A0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 BW
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DS1254
RAM READ MODE
The DS1254 executes a read cycle whenever WE is inactive (high) and CE is active (low). The unique address specified by the 21 address inputs (A0-A20) defines which of the 2M bytes of data is to be accessed. Valid data will be available to the eight data output drivers within tACC (Access Time) after the last address input is stable, providing that CE and OE access times and states are also satisfied. If OE and CE access times are not satisfied, then data access must be measured from the later occurring signal ( CE or OE ) and the limiting parameter is either tCO for CE or tOE for OE rather than address access.
RAM WRITE MODE
The DS1254 is in the write mode whenever WE and CE are in their active (low) state after address inputs are stable. The later occurring falling edge of CE or WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time (tWR) before another cycle can be initiated. The OE control signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output bus has been enabled ( CE and OE active) then WE will disable the outputs in tODW from its falling edge.
DATA RETENTION MODE
The device is fully accessible and data can be written and read only when VCC is greater than VPF. However, when VCC falls below the power fail point VPF (point at which write protection occurs) the internal clock registers and SRAM are blocked from any access. When VCC falls below VBAT, device power is switched from the VCC to VBAT. RTC operation and SRAM data are maintained from the battery until VCC is returned to nominal levels. All signals must be powered down when VCC is powered down.
PHANTOM CLOCK OPERATION
Communication with the Phantom Clock is established by pattern recognition on a serial bit stream of 64 bits which must be matched by executing 64 consecutive write cycles containing the proper data on DQ0. All accesses which occur prior to recognition of the 64-bit pattern are directed to memory. After recognition is established, the next 64 read or write cycles either extract or update data in the Phantom Clock, and memory access is inhibited. Data transfer to and from the timekeeping function is accomplished with a serial bit stream under control of Chip Enable ( CE ), Output Enable ( OE ), and Write Enable ( WE ). Initially, a read cycle to any memory location using the CE and OE control of the Phantom Clock starts the pattern recognition sequence by moving a pointer to the first bit of the 64-bit comparison register. Next, 64 consecutive write cycles are executed using the CE and WE signals of the device. These 64 write cycles are used only to gain access to the Phantom Clock. Therefore, any address within the first 512 kbytes of memory, (00h to 7FFFFh) is acceptable. However, the write cycles generated to gain access to the Phantom Clock are also writing data to a location in the memory. The preferred way to manage this requirement is to set aside just one address location in memory as a Phantom Clock scratch pad. When the first write cycle is executed, it is compared to bit 0 of the 64-bit comparison register. If a match is found, the pointer increments to the next location of the comparison register and awaits the next write cycle. If a match is not found, the pointer does not advance and all subsequent write cycles are ignored. If a read cycle occurs at any time during pattern recognition, the present sequence is aborted and the comparison register pointer is reset.
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DS1254
Pattern recognition continues for a total of 64 write cycles as described above until all the bits in the comparison register have been matched (this bit pattern is shown in Figure 2). With a correct match for 64-bits, the Phantom Clock is enabled and data transfer to or from the timekeeping registers can proceed. The next 64 cycles will cause the Phantom Clock to either receive or transmit data on DQ0, depending on the level of the OE pin or the WE pin. Cycles to other locations outside the memory block can be interleaved with CE cycles without interrupting the pattern recognition sequence or data transfer sequence to the Phantom Clock.
PHANTOM CLOCK REGISTER INFORMATION
The Phantom Clock information is contained in eight registers of 8-bits, each of which is sequentially accessed one bit at a time after the 64-bit pattern recognition sequence has been completed. When updating the Phantom Clock registers, each register must be handled in groups of 8-bits. Writing and reading individual bits within a register could produce erroneous results. These read/write registers are defined in Figure 3.
PHANTOM CLOCK PROTOCOL DEFINTION Figure 2
NOTE:
The pattern recognition in Hex is C5, 3A, A3, 5C, C5, 3A, A3, 5C. The odds of this pattern being accidentally duplicate and causing inadvertent entry to the Phantom Clock is less than 1 in 1019. This pattern is sent to the Phantom Clock LSB to MSB.
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DS1254
PHANTOM CLOCK REGISTER DEFINTION Figure 3
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AM-PM/12/24 MODE
Bit 7 of the hours register is defined as the 12- or 24-hour mode select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20-23 hours).
OSCILLATOR BIT
Bit 5 of the day register controls the oscillator. When set to logic 1, the oscillator is off. When set to logic 0, the oscillator turns on and the watch becomes operational.
ZERO BITS
Registers 1, 2, 3, 4, 5, and 6 contain one or more bits which will always read logic 0. When writing these locations, either a logic 1 or 0 is acceptable.
BATTERY MONITORING
The DS1254 automatically monitors the battery in an attached DS3800 Battery Cap on a 24-hour time interval. Such monitoring begins within tREC after VCC rises above VPF and is suspended when power failure occurs. After each 24-hour period has elapsed, the battery is connected to an internal 1 M test resistor for one second. During this one second, if the battery voltage falls below the battery voltage trip point (~2.6V), the battery warning output BW is asserted. Once asserted, BW remains active until the attached DS3800 Battery Cap is replaced. However, the battery is still re-tested after each VCC power-up, even if was active on power-down. If the battery voltage is found to be higher than ~2.6V during such testing, BW is de-asserted and regular testing resumes. BW has an open-drain output driver.
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DS1254
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature -0.3V to +6.0V 0C to +70C -40C to +70C See J-STD-020A specification
* This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER Power Supply Voltage (5V operation) Power Supply Voltage (3.3V operation) Logic 1 Voltage All Inputs VCC = 5V10% VCC = 3.3V10% Logic 0 Voltage All Inputs VCC = 5V10% VCC = 3.3V10% SYMBOL VCC VCC VIH VIH VIL VIL MIN 4.5 3.0 2.2 2.0 -0.3 -0.3 TYP 5.0 3.3 MAX 5.5 3.7 VCC+0.3 VCC+0.3 0.8 0.6
(0C to 70C)
UNITS V V V V V V NOTES 1 1 1 1 1 1
DC ELECTRICAL CHARACTERISTICS
PARAMETER Input Leakage Current I/O Leakage Current Output Current @ 2.4V Output Current @ 0.4V Standby Current CE = 2.2V Standby Current CE = VCC-0.5V Operating Current, tCYC = 100 ns Write Protection Voltage SYMBOL IIL IIO IOH IOL ICCS1 ICCS2 ICCO1 VPF MIN -4.0 -4.0 -1.0 2.0
(0C to 70C; VCC = 5.0V10%)
TYP MAX +4.0 +4.0 UNITS A A mA mA mA mA mA V NOTES
3 3
5.0 3.0 4.25
10 5.0 85 4.50
1
DC ELECTRICAL CHARACTERISTICS
PARAMETER Input Leakage Current I/O Leakage Current Output Current @ 2.4V Output Current @ 0.4V Standby Current CE = 2.2V Standby Current CE = VCC-0.5V Operating Current, tCYC = 100 ns Write Protection Voltage SYMBOL IIL IIO IOH IOL ICCS1 ICCS2 ICCO1 VPF MIN -4.0 -4.0 -1.0 2.0
(0C to 70C; VCC = 3.3V10%)
TYP MAX +4.0 +4.0 UNITS A A mA mA mA mA mA V NOTES
3 3
5.0 2.0 2.8
7 3.0 50 2.97
1
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DS1254
CAPACITANCE
PARAMETER Input Capacitance: A0-A18, OE , WE , CE Input Capacitance: A19-A20 I/O Capacitance: DQ0-DQ7 Output Capacitance: BW SYMBOL CIN CIN CIO COUT MIN TYP 25 5 25 5 MAX 50 10 50 10
(TA = 25C )
UNITS pF pF pF pF NOTES
AC ELECTRICAL CHARACTERISTICS
PARAMETER Read Cycle Time Address Access Time OE to Output Valid to Output Valid CE or OE to Output Active Output High Z from Deselection Output Hold from Address Change Write Cycle Time WE , CE Pulse Width Address Setup Time Address Hold Time
CE
(0C to 70C; VCC = 5.0V10%)
MIN 100 MAX 100 55 100 5 35 5 100 70 0 5 25 35 5 40 0 20 20 20 UNITS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS NOTES
SYMBOL tRC tAAC tOE tCO tCOE tOD tOH tWC tWP tAW tAH1 tAH2 tODW tOEW tDS tDH1 tDH2 tRR tWR
2 2
5 6 7 2 2 8 6 8
Output High Z from WE Output Active from WE Data Setup Time Data Hold Time Read Recovery (Clock Access Only) Write Recovery (Clock Access Only)
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DS1254
AC ELECTRICAL CHARACTERISTICS
PARAMETER Read Cycle Time Address Access Time OE to Output Valid CE to Output Valid CE or OE to Output Active Output High Z from Deselection Output Hold from Address Change Write Cycle Time WE , CE Pulse Width Address Setup Time Address Hold Time Output High Z from WE Output Active from WE Data Setup Time Data Hold Time Read Recovery (Clock Access Only) Write Recovery (Clock Access Only) SYMBOL tRC tAAC tOE tCO tCOE tOD tOH tWC tWP tAW tAH1 tAH2 tODW tOEW tDS tDH1 tDH2 tRR tWR MIN 150
(0 C to 70 C; VCC = 3.3V10%)
MAX 150 75 150 5 70 5 150 100 0 5 25 70 5 60 0 20 20 20 UNITS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS NOTES
2 2
5 6 7 2 2 8 6 8
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DS1254
MEMORY READ CYCLE TIMING Figure 4
tRC ADDRESS
tACC CE tCO tOD OE tOE
tOH
tCOE DQ0-DQ7
tCOE
tOD output data valid
See Note 9
MEMORY WRITE CYCLE TIMING, WRITE ENABLE CONTROLLED Figure 5
tWC ADDRESS
tAW CE tAH1 WE tWP
tODW
tOEW
DQ0-DQ7
tDS data in stable
tDH1
See Notes 5, 6, 8, 10, 11, 12, and 13
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DS1254
MEMORY WRITE CYCLE TIMING, CHIP ENABLE CONTROLLED Figure 6
tWC ADDRESS
tAW CE
tWP
tAH2
WE tODW
tCOE
DQ0-DQ7
tDS data in stable
tDH2
See Notes 5, 7, 8, 10, 11, 12, and 13
READ CYCLE TO PHANTOM CLOCK Figure 7
tRC WE = VIH CE tCO tOD OE tOE tCOE tOD output data valid tRR
tCOE DQ0
WRITE CYCLE TO PHANTOM CLOCK Figure 8
OE = VIH tWP WE TAH2 CE tWP tWC tWR
tDS
tDH2 tDH1 data in stable
DQ0
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DS1254
POWER UP/DOWN WAVEFORM TIMING Figure 9
VCC VPF(max) VPF(min) VBAT tPD tF
tFB tDR tR Slews with VCC
tREC
CE , WE
Slews with VCC
tBPU
BW
See Note 14
POWER UP/DOWN CHARACTERISTICS
PARAMETER CE and WE at VIH Before Power Down VCC Fall Time: VPF(max) to VPF(min) VCC Fall Time: VPF(min) to VBAT VCC Rise Time: 0V to VPF(min) VCC Valid to End of Write Protection VCC Valid to BW Valid SYMBOL tPD tF tFB tR tREC tBPU MIN 0 300 10 150 TYP MAX
(VCC = 5V10%)
UNITS S S S S mS Sec NOTES
125 1
3
(TA = 25C )
PARAMETER Expected Data Retention Time (Oscillator On) SYMBOL tDR MIN 10 TYP MAX UNITS years NOTES 4
WARNING:
Under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery backup mode.
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DS1254
BATTERY WARNING DETECTION Figure 10
VCC tBPU VBAT 2.6V tBTC tBTPW
BATTERY TEST ACTIVE
tBW BW
See Note 3
BATTERY WARNING TIMING
PARAMETER Battery Test Cycle Battery Test Pulse Width Battery Test to BW Active VCC Valid to BW Valid SYMBOL tBTC tBTPW tBW tBPU MIN
(0C to 70C; VCC = 5.0V10%)
TYP 24 MAX 1 1 1 UNITS hr Sec Sec Sec NOTES
3
AC TEST CONDITIONS
Output Load: 100 pF + 1 TTL Gate Input Pulse Levels: 0.0V to 3.0V Timing Measurement Reference Levels: Input: 1.5V Output: 1.5V Input Pulse Rise and Fall Times: 5 nS
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DS1254
NOTES:
1. Voltage referenced to ground. 2. These parameters are sampled with a 50 pF load and are not 100% tested. 3. BW is an open drain output and, as such, cannot source current. An external pullup resistor should be connected to this pin for proper operation. BW can sink 10 mA. 4. The DS3800 Battery Cap is a one time use part, but can be removed and replaced. By Design, removal of a DS3800 will mechanically damage the Battery Cap which eliminates the accidental use of a previously attached and possibly low capacity Battery Cap. 5. tWP specified as the logical AND of CE and WE , tWP is measured from the latter of CE or WE going low to the earlier of CE or WE going high. 6. TAH1, tDH1 are measured from WE going high.. 7. TAH2, tDH2 are measured from CE going high. 8. tDS is measured from the earlier of CE or WE going high. 9. WE is high for a read cycle. 10. OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high impedance state. 11. If the CE low transition occurs simultaneously with or later than the WE low transition in a write enable controlled write cycle, the output buffers remain in a high impedance state during this period. 12. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain in a high impedance state during this period. 13. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers remain in a high impedance state during this period. 14. In a power down condition, the voltage on any pin may not exceed the voltage on VCC.
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DS1254
DS1254 PACKAGE DIMENSIONS
Min 1.570 39.88 1.570 39.88 0.033 0.84 1.497 38.02 0.047 1.19 0.033 0.84 0.047 1.19 0.234 5.94 0.125 3.10 0.025 0.64 Max 1.580 40.13 1.580 40.13 0.043 1.09 1.503 38.18 0.053 1.35 0.043 1.09 0.053 1.35 0.240 6.10 0.135 3.43 ? ? 0.030 0.76
A B C D E F G H I J K
in mm in mm in mm in mm in mm in mm in mm in mm in mm in mm in mm
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DS1254
DS1254 PACKAGE DIMENSIONS (WITH ATTACHED DS3800 BATTERY CAP)
Min 1.656 42.06 1.656 42.06 Max 1.668 42.37 1.668 42.37 0.485 12.32
A
in mm B in mm C in mm
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DS1254
DS1254 RECOMMENDED LAND PATTERN (with overlaid Package Outline)
The DS1254 ball grid array is a subset of the industry-standard 40 mm BGA format, with all balls on a 50-mil grid. Corner balls have been removed to provide space for the electrical and mechanical interface features that facilitate attachment of the DS3800 Battery Cap.
Note *
0.250
0.500
0.150
* Note: Ground shield to isolate RTC XTAL from EMI
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